Conventionally, to cope with an increase in the number of signals due to enhancement of the function of LSI, semiconductor devices of the QFP (Quad Flat Package) type are being developed. In the semiconductor device of the QFP type, since wire bonding is implemented between inner leads of a lead frame and electrodes of a semiconductor chip on a basis of one-to-one correspondence, the number of terminals that can be drawn from the semiconductor chip to the outside of the package is substantially equal to the number of inner leads, that is, the number of external terminals (pins) of the package. Therefore, in a semiconductor device incorporating a semiconductor chip requiring a number of electrodes for power supply and electrodes for grounding, the number of external terminals is increased to cope with the increase in the number of electrodes of the semiconductor chip. However, the increase in the number of external terminals leads to a problem of increasing the package size.
Further, a QFP has been proposed which is structured such that common leads (first common leads) wire-bonded to electrodes of a semiconductor chip are arranged around a chip mounting portion, second common leads each having supporting leads on its both ends and wire-bonded thereto are disposed, and resin sealing is performed (see, for example, JP-A 2007-180077 (KOKAI)).
However, in the semiconductor device in such a structure, wires (bonding wires) have been susceptible to deformation and damage due to non-uniformity in arrangement of the common leads in a molding process of a resin sealed body. Further, the leads have not always been optimally arranged, causing a problem of difficulty in reducing the inductance.